The present invention relates to phase locked loop systems, and more particularly to a sampling phase detector for a divide-by-n phase locked loop system that substantially reduces phase noise and spurious phase modulation components at harmonics of a sampling frequency.
There is a continual need for circuit arrangements that provide a second signal in accurately timed relationship with a first signal. Phase locked loops are commonly used to accomplish this end. In a phase locked loop the two signals are applied to a phase detector, the output of which is a function of the phase difference between the two signals. An error voltage is developed that is applied to the control input of a voltage controlled oscillator after lowpass filtering in a loop filter to make the oscillator signal phase follow a reference signal phase. Although in most second order phase locked loops an error amplifier is inserted between the phase detector and the voltage controlled oscillator, as shown in U.S. Pat. No. 4,316,150 issued Feb. 16, 1982 to Philip S. Crosby entitled "Phase Locked Loop Including Phase Detector System Controlled by Enable Pulses", the error amplifier may be omitted, reducing one source of phase and frequency noise fluctuations.
However in the prior Crosby phase locked circuit an undesired signal component at the repetition frequency of the enable pulses, and harmonics thereof, is produced. The amplitude of this undesired signal component is proportional to the square of the width of the enable pulse and contributes an undesired fluctuation in the frequency of the voltage controlled oscillator if the phase locked loop bandwidth is sufficiently large and/or the enable pulse is sufficiently wide. Furthermore the transistors that provide the output signal to the loop filter must have an area commensurate with the current being switched as well as an operating speed commensurate with the width of the enable pulse. These requirements may not be compatible with other desired device parameters, namely, minimal leakage currents and levels of shot noise.
What is desired is a sampling phase detector that has reduced levels of undesired signal components to permit increased loop bandwidth and capture range, that has reduced output device area to permit lower levels of leakage current, thereby reducing static offsets, and that has reduced operating speed of the output devices to permit the use of devices having a reduced noise level.